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VectorCombine's foldShuffleOfCastops narrows shuffle(zext x) into zext(shuffle x) across the shuffles Halide uses to split vectors into native-width pieces. On AArch64 with LLVM 22+ this produces illegal narrow types (e.g. <4 x i8>) that lower to mov/zip/bic sequences instead of ushll2/umull2, e.g. for u32(u8) * 1000. On ARM, VectorCombine's benefit across the apps is negligible (hot inner loops are net neutral), so skip it there via a pass instrumentation callback. Other targets are unaffected. Also add sshll2/ushll2 checks to simd_op_check_arm. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
## main #9699 +/- ##
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+ Coverage 72.89% 72.95% +0.05%
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Files 266 266
Lines 83478 83483 +5
Branches 20497 20498 +1
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+ Hits 60855 60905 +50
- Misses 16173 16180 +7
+ Partials 6450 6398 -52 ☔ View full report in Codecov by Harness. 🚀 New features to boost your workflow:
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LLVM main passes an IRUnitRef rather than an llvm::Any. Take the IR unit as a generic const reference, which also satisfies clang-tidy. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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Copilot says:
This is an alternative to #9698.
On AArch64 with LLVM 22 and later, LLVM's VectorCombine pass (
foldShuffleOfCastops) narrowsshuffle(zext x)intozext(shuffle x)across the shuffles Halide uses to split vectors into native-width pieces. This produces illegal types like<4 x i8>, which lower tomov/zip/bicsequences instead ofushll2/umull2. For example,u32(u8) * 1000and a plainu32(u8)both hit this. #9698 works around this incall_intrin, but that fix relies on cost-model details and misses the plain-zext case. LLVM 21 doesn't have the problem.This PR skips VectorCombine on ARM targets only, using a pass instrumentation callback on Halide's
PassBuilder. It doesn't use the global-disable-vector-combineoption, so other targets compiled in the same process are unaffected. The change is small and should backport cleanly to releases pinned to an older LLVM.Tested with LLVM 23:
ushll/ushll2+umull(2)/umlal(2), ortblfor the zext-only case.fmov/mov.correctness_simd_op_check_armpasses, including newsshll2/ushll2checks.Checklist